Broadcom PEX88T32 Retimer: When Does a PCIe 4.0 Design Need One?
Broadcom PEX88T32 Retimer: When Does a PCIe 4.0 Design Need One?
Quick answer: Consider the Broadcom PEX88T32 when a PCIe 4.0 x16 connection has a difficult signal path through a long PCB route, connectors, a backplane or a cable. It conditions and retimes the link between a host and an I/O device or subsystem. If the objective is to connect one host to multiple endpoints, the design instead needs a PCIe switch and may also need retimers on long links.
Where does the PEX88T32 fit?
Broadcom specifies the PEX88T32 as a 32-lane bidirectional PCIe 4.0 retimer: 16 lanes toward one side of the link and 16 lanes toward the other. It supports PCIe generations 1 through 4. A typical placement is partway between a CPU and an I/O device on a long board, at the edge of a board connecting to a cable, or along a backplane or mezzanine-card path. Its standard ordering code is SS08-0B00-00. The 32-lane count describes the two sides of the retimed path; it does not mean that one x16 host connection becomes two independent x16 device connections.
Retimer or PCIe switch?
| Design question | Likely component | Reason |
|---|---|---|
| Does an existing x16 link need help reaching across a long board, cable or backplane? | PEX88T32 retimer | Addresses signal integrity on the link while preserving its connection purpose. |
| Must one host connect to several NVMe drives or other PCIe endpoints? | PCIe switch | Provides fan-out and port configuration; the retimer does not create extra endpoint ports. |
| Does a switched design also contain long or lossy PCIe links? | Switch plus retimer, if validated | The switch provides topology; retimers can be added where link analysis identifies a need. |
Broadcom lists receiver equalization, clock-data recovery, lane margining and loopback among the PEX88T32 features. Its brief also cites operation with up to 39 dB channel loss under specified conditions. Treat this as a device capability described in the product brief, not a guaranteed cable length or a substitute for your own channel simulation and interoperability testing.
What should engineers check before selecting it?
Map the complete channel: PCB traces, vias, connectors, backplane and cable, including both sides of the proposed retimer location.
Confirm the link arrangement: required x16 path, clocking approach and placement. Broadcom documents support for common clock, SRIS and SRNS configurations.
Plan configuration and validation: check whether Serial Boot ROM settings and optional error-containment features are needed; test the final host, retimer, cable and endpoint combination. Account for added retimer latency in timing-sensitive designs.
For switch-based fan-out, browse our Broadcom PCIe switch selection page. For a higher-generation switch design, see our Broadcom PEX89000 PCIe 5.0 overview; a Gen4-only PEX88T32 should not be assumed suitable for a Gen5 link. To request the PEX88T32, send an RFQ with SS08-0B00-00, quantity, target delivery date and the intended application. Confirm availability and lead time for the exact device.
